1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit.
2. Description of Related Art
Recently, a PLL circuit has been used on chip for clock signal distribution in an application-specific integrated circuit (ASIC), a microcomputer or the like used in various devices. There is a large variety of characteristics required for a PLL circuit. For example, a PLL circuit including a loop filter with a high cut-off frequency is used when it is intended to shorten lock-up time, and a-PLL circuit including a loop filter with a low cut-off frequency is used when it is intended to suppress jitter of an input clock from being transferred to an output clock. In this manner, it is desired to implement a PLL circuit that generates a clock signal in compliance with the characteristics required according to circumstances.
FIG. 6 shows a block configuration of a PLL circuit 1 that includes a loop filter according to prior art disclosed in Japanese Patent No. 3840468. Referring to FIG. 6, the PLL circuit 1 includes a phase frequency detector 10, switch circuits SW10 and SW20, loop filters FIL10 and FIL20, a voltage control oscillator 20, a frequency divider 30, and a control circuit 40.
The phase frequency detector 10 compares the phases of a clock signal input from an input terminal IN1 and a clock signal output from the frequency divider 30. The phase frequency detector 10 then outputs a current signal VC corresponding to a phase difference between the clock signals to the loop filter FIL10 or FIL20 via the switch circuit SW10.
The loop filters FIL10 and FIL20 have different cut-off frequencies. The loop filters FIL10 and FIL20 convert the current signal output from the phase frequency detector 10 to a voltage signal. The loop filters FIL10 and FIL20 then output the voltage signal VCS to the voltage control oscillator 20 via the switch circuit SW20. It is assumed in this example that the cut-off frequency of the loop filter FIL10 is lower than the cut-off frequency of the loop filter FIL20.
The voltage control oscillator 20 generates a clock signal OUT with a frequency corresponding to the voltage signal VCS output from the loop filter FIL10 or FIL20 and outputs it to an output terminal OUT.
The frequency divider 30 divides the frequency of the clock signal OUT output from the voltage control oscillator 20 by a predetermined value. The frequency divider 30 then outputs a feedback clock signal FD after frequency division to the phase frequency detector 10.
One end of a variable capacitor C1 is connected to the output terminal OUT, and the other end is connected to a ground terminal GND. The variable capacitor C1 is a capacitor whose capacitance can be changed, and the capacitance is changed in response to control by the control circuit 40.
The control circuit 40 controls the switch circuits SW10 and SW20 based on a signal input from an input terminal IN2 and selects one of the loop filters FIL10 and FIL20. By selecting either the loop filter FIL10 or FIL20 to be connected, the PLL circuit 1 can operate With the characteristics required in a system. For example, when selecting the loop filter FIL20 with a high cut-off frequency, it is possible to shorten the lock-up time. On the other hand, when selecting the loop filter FIL10 with a low cut-off frequency, it is possible to suppress jitter of a signal input to the PLL circuit 1 from being transferred to an output signal.
FIG. 7 is an exemplary block diagram of the phase frequency detector 10 used in the PLL circuit 1. Referring to FIG. 7, the phase frequency detector 10 includes a phase comparison circuit 11 and a charge pump 12. The phase comparison circuit 11 receives a clock signal FR from the input terminal IN1 and a feedback signal FD and outputs pulse signals UP and DN. The charge pump 12 receives the pulse signals UP and DN and outputs a current signal VC.
FIG. 8 shows an exemplary circuit configuration of the charge pump 12. The charge pump 12 includes a current generation unit 13 and an output driver unit 14. The current generation unit 13 includes a first current source circuit made up of a current source IS11 and an NMOS transistor MN11 and a second current source circuit made up of a current source IS21 and a PMOS transistor MP21. The output driver unit 14 includes a current output PMOS transistor MP23, a current output NMOS transistor MN13, switch circuits SW11 and SW21, a pull-up PMOS transistor MP22, and a pull-down NMOS transistor MN12. The on/off of the switch SW11 is controlled according to the pulse signal DN. By the switch SW11, the on/off of the current output NMOS transistor MN13 is controlled. The on/off of the switch SW21 is controlled according to the pulse signal UP. By the switch SW21, the on/off of the current output PMOS transistor MP23 is controlled,
FIG. 9 is an exemplary block diagram of the voltage control oscillator 20 used in the PLL circuit 1. Referring to FIG. 9, the voltage control oscillator 20 includes a voltage-current conversion circuit 21 and a current control oscillator 22. The voltage-current conversion circuit 21 receives the voltage signal VCS and outputs a current signal IC to the current control oscillator 22. The current control oscillator 22 outputs a clock signal OUT with a frequency corresponding to the current signal IC.
FIG. 10 shows an exemplary circuit configuration of the voltage-current conversion circuit 21. The voltage-current conversion circuit 21 includes an input NMOS transistor MN31, a pull-down NMOS transistor MN32, and a resistor R31. The input NMOS transistor MN31 receives the voltage signal VCS at its gate and outputs the current signal IC to its drain. The pull-down NMOS transistor MN32 supplies a ground voltage for turning off the input NMOS transistor MN31 to the gate of the input NMOS transistor MN31 upon receiving a standby signal at its gate.
The operation of the PLL circuit 1 according to prior art is described hereinbelow. If a signal input from the input terminal IN2 is configured so as to lock up the PLL circuit 1 at high speed, for example, the control circuit 40 controls the switch circuits SW10 and SW20 and selects the loop filter FIL20. The phase frequency detector 10 compares the phases of the signal FR input from the input terminal IN1 and the feedback clock signal FD output from the frequency divider 30. Then, the loop filter FIL20 converts the current signal VC corresponding to the phase difference to the voltage signal VCS. The voltage signal VCS is input to the voltage control oscillator 20; and the voltage control oscillator 20 outputs the clock signal OUT with a frequency corresponding to the voltage signal VCS. The frequency divider 30 divides the frequency of the clock signal OUT by a predetermined value and outputs the feedback signal FD to the phase frequency detector 10.
On the other hand, if a signal input from the input terminal IN2 is configured so as to suppress transfer of jitter of an input clock to the PLL circuit 1, for example, the control circuit 40 controls the switch circuits SW10 and SW20 and selects the loop filter FIL10. The phase frequency detector 10 compares the phases of the signal FR input from the input terminal IN1 and the feedback signal FD output from the frequency divider 30. Then, the loop filter FIL10 converts the current signal VC corresponding to the phase difference to the voltage signal VCS. The voltage signal VCS is input to the voltage control oscillator 20, and the voltage control oscillator 20 outputs the clock signal OUT with a frequency corresponding to the voltage signal VCS. The frequency divider 30 divides the frequency of the clock signal OUT and outputs the feedback signal FD to the phase frequency detector 10.
With use of the PLL circuit 1 as described above, when it is desirable to selectively use a PLL circuit with a different cut-off frequency in a semiconductor integrated circuit such as an ASIC, for example, it is possible to operate a PLL circuit with a desired cut-off frequency by switching loop filters with a switch circuit, without preparing a plurality of PLL circuits.